The present invention relates to the fabrication of junction diodes, particularly to a process for forming thin-film silicon junction diodes on a thin metal film, and more particularly to direct integration of a thin-film silicon p-n junction diode with a magnetic tunnel junction for use in advanced magnetic random access memory cells, such as used for high-performance, non-volatile memory.
Magnetic random access memory (MRAM) using giant magneto-resistance (GMR) materials and spin-dependent tunneling (MTJs) has been developed for high-performance, non-volatile memory. Such memory cells have significant advantage over previous state-of-the-art in that they are current-perpendicular-to-plane (CPP) devices, that is, sense current flows perpendicularly from word-to-bit line through the memory, whereas, in previous configurations, sense current flowed in the plane (CIP) of the memory element. The CPP configuration results in a number of advantages including minimum size cell and ease of dimensional scaling with semiconductor feature sizes. The basic magnetic storage element in a CPP MRAM cell consists of two magnetic multilayers (GMR films) separated by a thin insulator (for instance Al2O3). The magnetization moments of the two films may be either parallel or anti-parallel, such alignment defining either a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d for the cell. These states are written by passing a write current through the word and bit line. This current, which should not flow through the cell, creates a magnetic field that switches the direction of the moment of one of the GMR layers. For the read process, a sense current is passed perpendicular through the cell, generating a voltage from the magneto-resistance of the cell. Thus, the magneto-resistance of the cell contains the information on the state of that cell.
For fabrication of a memory from these cells, the cells are placed between word and bit line intersections, forming an array of nxn cells. To write or read a cell, ni, the word and bit lines whose intersection occurs at ni are activated. However, since the cells are essentially resistors, problems arise in read and write sensitivity as a result of shunt currents passing through cells other than ni. Such problems are eliminated by placing an electronic switch between the word and bit lines in series with each magnetic cell. Such a device can be a diode or transistor whose impedance is controlled by differences between the word and bit line voltages.
Accordingly, there is a need for providing this electronic switch between word and bit lines in series with the magnetic cell. There is also a need for developing a fabrication process allowing the construction of a silicon diode or transistor directly onto a metal word or bit line that can be manufactured. There is also a need for this process to be low temperature, so as to not affect the metal word or bit lines or underlying or adjacent Si electronics.
The present invention provides a solution to the above needs wherein the needs are met by direct vertical integration of a diode or transistor (voltage controlled switch) with the MTJ stack between the word and bit lines. This process is carried out without thermal damage to the underlying Complementary Metal Oxide Semiconductor Integrated Circuit (CMOS IC) circuitry by using appropriate low temperature deposition steps in conjunction with a pulsed energy source for melting, recrystallizing, and doping the deposited amorphous Si films. This allows formation of the p-n junction or TFT directly onto the surface of the word/bit lines.
It is an object of the present invention to provide a non-linear element (switch) between two metal conductors in an electric circuit that is fabricated directly onto one of the metal conductors.
A further object of the invention is to provide a process allowing the construction of a silicon diode or transistor directly onto a metal word or bit line, without damage to underlying or adjacent components.
Another object of the invention is to provide a process, based on pulsed laser processing, for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metal deposited on low temperature-substrates, such as ceramics, dielectrics, glass, or polymers.
Another object of the invention is to provide a process for direct integration of a thin-film, Si p-n junction diode, or transistor, with a magnetic tunnel junction stack for use in advanced, high-performance magnetic random access memory cells.
Other objects and advantages of the present invention will become apparent from the following description and accompanying drawings.
The process of the present invention is suitable for implementation of current-perpendicular-to-plane (CPP) magnetic tunnel junction memory cells (MTJs) for use in non-volatile, high-performance, high-density magnetic random access memories. Such a memory cell consists of a magnetic storage device connected in series with a current control device such as a diode or transistor whose purpose is to control the current in the cell. Such cells are described in detail in U.S. Pat. No. 5,640,343 and 5,838,608. The purpose of this current control device is to provide selectivity in the read process for a selected cell (i.e., preventing unwanted currents from flowing through other unselected cells and causing erroneous read signals) and to isolate the selected memory cell from write currents used in the write process. The process allows direct integration of the current control element vertically with the magnetic element at low temperatures. This allows fabrication of the memory cell at the crossing of the word and bit lines, resulting in a minimum size, scalable configuration.
The process is based on pulsed laser processing, for the fabrication of vertical polycrystalline silicon electronic device structures, in particular p-n junction diodes, on films of metal deposited onto low temperature-substrates such as ceramics, dielectrics, glass, or polymers. The process preserves underlayers and structures onto which the devices are typically deposited, such as silicon integrated circuits. The process involves the low temperature deposition of one or several layers of silicon, either in an amorphous or a polycrystalline phase. Dopants may be introduced in the film during or after the Si deposition from the gas phase, by normal deposition processes, by plasma processes, or by ion implantation. The films are then irradiated with a short-pulse energy source that is efficiently absorbed in the Si, such as provided by a XeCl excimer laser. This results in the crystallization of the film and simultaneously in the activation of the dopants via ultrafast melting and solidification. The films can also be crystallized and doped by heating an over layer film with the energy source to a temperature that results in melting and recrystallization of the underlying amorphous or poly-Si films. The silicon films can be patterned either before or after crystallization. The fabrication process also involves low temperature deposition of various metal films, such as W and Mo, and dielectric layers, such as SiO2 or Si3N4, for device and circuit fabrication purposes.
The process involves a non-linear element (switch) between two metal conductors in an electrical circuit that is fabricated directly onto one of the metal conductors. Potential use in certain types of magnetic memory cells relying on current perpendicular to the device plane, integration into integrated circuits, replace discrete non-linear elements for electronic applications. Provide thin film transistor structures and diode structures, both lateral and vertical to fabricate poly-Si thin film electronics on a wide variety of substrates, such as finished integrated circuits, metal lines, layers, ceramic films, and layers. An example device enabled by this technology is the vertical magnetic tunnel junction cell for fabrication of non-volatile, low power memory. This cell has immediate potential to replace E2-PROM, presently considered a major semiconductor memory technology.